Question

薄荷草

求救啊QQ

一一~ /

三、MWOS7E了了

工efs wo表 ouf Moore:s Jaw, which states the 人

  
 
  
   

7PD-fype Subsfrafe
(58ody)Cpanmnel
吧 和  Tegion

,                 Drain reglon      f
“Fi9. 3-1 (LeftA planar MOSFET; (Right) a FinFET

Metal (gate)           0

|                   Oxide
nmrsource   1 nm p-Si       nm+ drain

SiO.

 

 

 

 

 

2

 

Si substrate

 

 

 

  

Fig. 3-2 An SOI Si MOSFET

(人) Bora egular MOSFET, to increase the transistor countina wafer without affecting

了e device performance (i.e. current level), we prefer to reduce the gate length. If the
gate length is reduced by a factor of V2 “with the same current level, how_many
兩ore transistors wil] you get on a wafer? This gives you why the next generation ofx
2
一nm一10nm 一 7mm 人當5nm 一 3nm). Assume the wafe size is much larger
也an 也e fransistor dimension. (2%)
了he channel regions for FinFET structures in a cross sectional view ofthe

他 EE by using Ka FinFET to replace a planar

 Re womt be any inversion carriers at

對(9

時  souree and dminregioms are right next to the gated

                                                                                                                                                                                                                                                                   
 
                                                                                                                                                                                                                          
                                                                                                                                                                                                                                            
                                                                                                                                                                                                                
                                                                                                                                                                                                                                    

  

ln 品汪 in the surface
j] HIHWe useaFinFET
We can keep the gat
Wave a gate length 0
吧gate length is 20 mm
We Tatio of transist0! 上

assumption ai (一

說

廳 We _ want to have the same Current for each _transistor。by Teducing te

dimension of channelto 5 nm Width, but keeping the same gate length, What is the
Iatio of transistor count if we increase the Fin height to 80 nm? (4%)
(四) 了plain why you need a p-type substrate_ for a a-MOSFET. Note you have to ansWer

Why zz Junctions_ between Source/substrate and drain/substrate are required. Further,

Wwhy_ cant we make a planar #-MOSFET on an type substrate_With 人source_ and
九drain? (6%)
(五)For now, we have a new structure_ called “ultrathin-body silicon-on-insulator

 

 

 

 

(UTBSOD”MOSFET (Fig. 3-2). The channel doping is p-type and 10 cm .Please

draw its depletion region and the channel region When the device is turned on. (4o)
(六)Fwe change the channel doping to ntype, unlike (四), its Still a ttansistor, EXplain

Why. We usually call it a junetionless transistor. IS it n-MOSFET qr D-MOSFET?
el region when the devices is ON. When the device is ON, is there

半導體物理

Answer 1

曾幾何時

嗯
雖然我不太確定你要問什麼
但是MOSFET的基本運作原理是
利用對gate通電(需大過門檻電壓)
超過這個電壓後底下會形成一個通道
使得電流可以從source→drain

薄荷草

題目不懂 他在問什麼 不是本科系的😱

曾幾何時

我雖然剛好是這個系的但是還沒修到固態物理😔

曾幾何時

只能用大一學的基礎解釋一點點

薄荷草

好~多謝😂