ページ1:

8-9, 8-9-1, 8-119.
無關於電源供應的MOS偏壓電路-抗電源雜訊的互控式電流鏡
what on earth
is this?
a better (?) kind of
Current
mirror
CECALL
basic
Current mirror
AMP
what is the problem of
basic
Current
mirror ?
See
above
plot
green part
if
Some kind of paver SPLY
have
noise
then,
Io
will have
noise
How to solve this
problem ?
Use
Some kind of CKIT to of 4k
to吸收電壓訊
(which is another pair of (P) cument min
mirror

ページ2:

Then, why is the top partition of this CKIT different w/
the bottom partition of this CKIT ?
MOS
Because
above
Q1, you can't
Connect
#
↳ will cause:
Vsgp
Vsda
Usp locked by Usgp can't
吸收雜訊
Mos
Why
Q3
is
#
connected
?
Vbias 3
because
Gate of Q4 need to have
Vbi RS 3
(to be alive)
50....
MOS
#
Connect
Q3
to provide Vias 3
How did work?
small!
VDD +4 VDD
CUZ G & D
same
Point
↑
Q3 is just
a Res
gm
大部份的雜訊Vo將由Q2 的DS
端來承擔
所以Q3G極有近似雜訊
因為Voo有雜訊, Ves有雜訊,所以輸出(給別人用的)電壓雜訊就被消掉了

ページ3:

BTW 輸出給別人用の電壓&ike:
3
Vbas
AMP
Mother CKIT
What is
the problem of
this
current
mirror ?
can't
determine I
(only can
know I₁ =12= 13 = 14)
due
to
Q4 可伸縮
2、
can't self-start
輸出電流の引出問題:
bin En
this two pair.
of carpet mirror is互控串接,相互
參考②複製,所以無法再直接水接放大器電路,因此輸出電流必須額外複製提出
→
due to:
to be alive → need
Qa be alive
(provide
current down)
Q4
to be alive
→ need Q3 be
alve
(Vans)
Os to be alive → need
Q2 be
alive
(provide
current down)
Q2 to be alve
need
Qi be alive
(Vbias)
fucked up XD
P3

ページ4:

89.2無關於電源供應的電流鏡 8-124
(一)
觀念說明
簡單來說,由兩組電流鏡所組成,互控式結構,可抵抗電源
(供應) 雜訊,其原理是利用一電流源來吸收電流變動
就其中的一組電流鏡來論,在等效上,另一組電流鏡已經
變成他的電流源,而不再直接是電源供應了,因此
促成了 supply - independent bias circuit 但其前提是
電晶體為導通狀態,方能有如此效果
其次為了讓此互控式電流鏡的電流值可確定,於是在G-5
迴路之中加入-電阻R來限
但是,此電阻R會讓VG512UG52
VGS A
ANY 111
↓
VG5211
故而導致Q2通道較淺於
如果安排成&1=Q2匹配
則將會發生正回授現象
PIL

ページ5:

Un Cox Vou
en cox (-4)*
unCox Vou
Vas
百
must be SAT.
Fight
down
left down
R-D
L-D
VG52<VGSI
R-brownch have R
R eat up voltage
14 >12
VGS
道
until
VG52↓
cut off
Izv
all current=0
left
right
食
effect
13= 12
7
14 = 13
Current mirror
I₁ = 14
Q4 is
of Q
current source
achire
VG↓
Io↓
Via
Via
achive I₁ = 12
Tim → to
甲
回
中
To samup: 當加源極電阻R之後:若讓結構尺寸Q1:02.則將是錯誤
③設計,其中2原因是Q2通道較淺於Q,而導電性較差所致
綠線:正回授(?)
Pla

ページ6:

We make
Q2 > Qi
To solve the problem (if Qi
Q2
Current
aka k₂>ki
(while maintain Q3 = Q4 due to left
and right
current must be the same)
赫蘭道調變效應時 Want fad 工
find I
底下
Vasi = VGS2 + I R
重點就是兩邊ves不一樣
兩邊 current 一樣
Vou₁+Vtn = Vou₂ +V+ + IR
Vovy = Vov = +IR
ID=
K2R²
[註 2318052 P2
2
Mn Cox (R²
電路可起動後的偏壓電流解(穩態)
w
-1)²
小言
1、we
Can know that if Qi=Q2 then
(
will be 1 and 10=0
Q2
when a is 較寬→ Jo only R. Cox and 外形比決定
→無關
Ven & Voo
(as Voo is big enough)
3. about gm 2
(why do we
need
gaz lol)
2
8m2= 2√k₂ 10 =
(-1)=(
)
5#, tt, not that by
外形比,
only depends
on
thus : is called
製程
constant Gm bias CKIT

ページ7:

"1
I
problem
M
to
Limit
the
Current"
+5
To solve
the
can't determine
add
a
if the pap
in
the CKIT
of
the
PIG
is characterized
4
by its
Exp relationship w/
a
Scale
Current
Is
六
6
assume
and Q₂ to
be
mached
&
Q3 Q4 Q5
to be mached
Show that
the
DC Current
I
determine by
IR-VT)
fad the value of R that
Yields a
Current
I= 10MA
++
for the BJT VER = 0.7V @ IE = 1mA
first skip bit 8-123
-5